1. Field of the Invention
The present invention relates to imaging cells and, more particularly, to a method of operating an array of active pixel sensor cells.
2. Description of the Related Art
Traditional film-based cameras are rapidly being replaced by digital cameras that utilize a large number of imaging cells to convert the light energy received from an image into electric signals that represent the image. One type of imaging cell that is used in digital cameras to capture the light energy from an image is an active pixel sensor cell.
FIG. 1 shows a diagram that illustrates a prior-art imaging circuit 100. As shown in FIG. 1, imaging circuit 100 includes an active pixel sensor cell 110 that has an n+/p− photodiode 112 and an n-channel reset transistor 114. The p− region of n+/p− photodiode 112 is connected to ground.
Reset transistor 114 has spaced-apart n-type source and drain regions 114A and 114B that are formed in a p-type material 114C. Source region 114A, which has an n+ region and an n-type lightly-doped source (nlds) region, is connected to the n+ region of photodiode 112, while drain region 114B, which has an n+ region and an n-type lightly-doped drain (nldd) region, is connected to a supply voltage VCC.
In addition, a channel region of p− material 114C is located between and contacts source and drain regions 114A and 114B. Further, reset transistor 114 includes a layer of dielectric material 114D, such as gate oxide, that lies over the channel region, and a gate 114E that is formed on dielectric layer 114D over the channel region to receive a reset pulse.
In addition, active pixel sensor cell 110 also includes an n-channel source-follower transistor 116 that has a drain connected to the supply voltage VCC, and a gate that is connected to the n+ region of photodiode 112 and source 114A of reset transistor 114. Cell 110 further includes an n-channel row select transistor 118 that has a drain connected to the source of source-follower transistor 116, and a gate connected to receive a select signal.
In addition to active pixel sensor cell 110, imaging circuit 100 also includes a bias circuit 120 that defines a bias current I. Bias circuit 120 includes a first bias transistor 122, a second bias transistor 124, and a current source 126. First bias transistor 122 has a gate, a drain connected to the source of select transistor 118, and a source connected to ground.
Second bias transistor 124 has a drain, a gate connected to the gate of first bias transistor 122, and a source connected to ground. Current source 126, in turn, has an input connected to the supply voltage VCC, and an output connected to the gates of bias transistors 122 and 124, and to the drain of transistor 124.
The operation of imaging circuit 100 is performed in five steps. The initial step of the five is a first reset step where cell 110 is reset by pulsing gate 114E of reset transistor 114 with a reset signal RS for a pulse width PW period of time to place a diode voltage V1, which has a first integration magnitude, on the n+ region of photodiode 112 and the gate of source-follower transistor 116. The first integration magnitude of the diode voltage V1 is equal to the supply voltage VCC less the threshold voltage Vt of reset transistor 114. Further, unless being pulsed by the reset signal RS to, for example, five volts, gate 114E of reset transistor 114 is held at ground.
Alternately, the first integration magnitude of the diode voltage V1 can be equal to the supply voltage VCC when the voltage of the reset signal RS is equal to the supply voltage VCC plus the threshold voltage Vt of reset transistor 114. The alternate approach provides additional dynamic range equal to the threshold voltage Vt of reset transistor 114 at the cost of generating an additional voltage level.
The second step of the five is an integration step where light energy, in the form of photons, strikes photodiode 112, thereby creating a number of electron-hole pairs. Photodiode 112 is designed to limit recombination between the newly formed electron-hole pairs. As a result, the photogenerated holes are attracted to ground via the p− region of photodiode 112, while the photogenerated electrons are attracted to the n+ region of photodiode 112 where each additional electron reduces the magnitude of the diode voltage V1 on the n+ region of photodiode 112. As a result, photodiode 112 converts the light energy into a charge that varies an electrical value.
The third step of the five is a read step where the reduced magnitude of the diode voltage V1 is read from cell 110 at the end of the integration period to determine a second integration magnitude of the diode voltage V1. The second integration magnitude, which is equal to VCC−Vt−VS, where VS represents the change in voltage due to the absorbed photons, is read by turning on row select transistor 118.
When row select transistor 118 is turned on, the reduced magnitude of the diode voltage V1 on the n+ region of photodiode 112 reduces the magnitude of a second voltage V2 on the source of source-follower transistor 116 which, in turn, places a third voltage V3 on the source of select transistor 118. The third voltage V3 on the source of select transistor 118 is then detected by conventional voltage detectors.
The fourth step of the five is a second reset step where cell 110 is reset by pulsing gate 114E of reset transistor 114 with the reset signal RS to again place the first integration magnitude of the diode voltage V1 on the n+ region of photodiode 112 and the gate of source-follower transistor 116. Ideally, the first integration magnitude of the second reset step is identical to the first integration magnitude of the first reset step, i.e., equal to the supply voltage VCC or the supply voltage VCC less the threshold voltage Vt of reset transistor 114.
The last step of the five is a second read step where the diode voltage V1 is again read from cell 110 to determine the first integration magnitude of the diode voltage V1. The first integration magnitude is read by again turning on row select transistor 118. When row select transistor 118 is turned on, the first integration magnitude of the diode voltage V1 on the n+ region of photodiode 112 sets the magnitude of the second voltage V2 on the source of source-follower transistor 116. This then sets the magnitude of the third voltage V3 on the source of select transistor 118. The first integration magnitude on the source of select transistor 118 is then detected by conventional voltage detectors.
The number of photons which were absorbed by photodiode 112 during the image integration period can then be determined by subtracting the second integration magnitude read at the end of the integration period from the first integration magnitude read following the second reset, thereby yielding the value VS, i.e., ((VCC−Vt)−(VCC−Vt−VS)).
Bias circuit 120, in turn, sinks the bias current I through the NMOS transistors 116, 118, and 122. The bias transistors 122 and 124 and current source 126 function as a current mirror, where a voltage V4 on the gates of transistors 122 and 124 sets a common gate-to-source voltage, such that bias current I is proportional to the magnitude of the current sourced by current source 126 (depending on the relative sizes of transistors 122 and 124).
One drawback of active pixel sensor cell 110 is that, when fabricated in a deep submicron process, such as a 0.18-micron process, cell 110 suffers from a substantially large dark current. The dark current is a leakage current that discharges (pulls down) the first integration magnitude of the diode voltage V1 placed on the n+ region of photodiode 112 when no light energy is present at all. In addition, the dark current gets worse as CMOS processes are further scaled down, where the gate oxide layer becomes thinner and the doping concentrations become heavier, due to the increased electric field across the gate oxide layer.
In older processes, such as 0.35-micron and 0.50-micron processes, the dark current was predominantly due to the leakage current across the pn junction of photodiode 112. However, in a deep submicron process, such as a 0.18-micron process, the gate induced drain leakage (GIDL) current of the cell now also becomes a significant component of the dark current.
The GIDL current is a strong drain-to-gate voltage (Vdg) dependent current which results from a high electric field across dielectric layer 114D of reset transistor 114 in the region where gate 114E vertically overlaps drain region 114B. When a high electric field is present, such as when ground is applied to gate 114E and the supply voltage VCC is applied to drain 114B at the beginning of an integration period, a deep depletion region is formed under gate 114E in the gate/drain overlap region which, in turn, generates electrons and holes by band-to-band tunneling at the silicon—silicon dioxide interface. The resulting drain-to-body current, which injects electrons into drain region 114B, forms the GIDL current.
The GIDL current IGIDL is roughly related to the ratio of the gate-to-drain voltage Vgd (Vgd is negative when reset transistor 114 is turned off) to the thickness of the dielectric layer 114D (Tox) and drain-to-body voltage (Vdb) as shown in EQ. 1:
                              I          GIDL                ∝                                            -                              V                gd                                                    T              ox                                ·                      exp            ⁡                          (                                                T                  ox                                                  V                  gd                                            )                                ·                                    V              db              3                                      α              +                              V                db                3                                                                        EQ        .                                  ⁢        1            where α represents a constant related to process, and g, d, and b represent the gate, drain, and body, respectively.
Since MOS transistors are symmetrical, a strong source-to-gate Vsg dependent current also results from a high electric field across dielectric layer 114D of reset transistor 114 in the region where gate 114E vertically overlaps source region 114A. As before, when a high electric field is present, such as when ground is applied to gate 114E and the supply voltage VCC (or VCC−Vt114) is applied to source 114A at the beginning of the integration period, a deep depletion region is formed under gate 114E in the gate/source overlap region which, in turn, generates electrons and holes by band-to-band tunneling at the silicon—silicon dioxide interface. The resulting source-to-body current, which injects electrons into source region 114A, forms a source GIDL current that discharges (pulls down) the first integration magnitude of the diode voltage V1 placed on the n+ region of photodiode 112.
Thus, when active pixel sensor cell 110 is exposed to the light energy from an image during an integration period, the first integration magnitude of diode voltage V1 placed on the n+ region of photodiode 112 falls in response to both the received light energy as well as the dark current, which includes a photodiode leakage component and a source GIDL component.
When the overall dark current is high, the minimum voltage that can be obtained increases which, in turn, reduces the dynamic range of cell 110. When the overall dark current is excessively high due to a large source GIDL current component, cell 110 can saturate before the end of the integration period which, in turn, renders the cell useless (bad). An active pixel sensor cell saturates when the combination of light energy and dark current pull the voltage on the n+ region of photodiode 112 down to ground before the image integration period has ended.
When an array of active pixel sensor cells is formed, the layer of dielectric material used with all of the reset transistors in the array, such as dielectric layer 114D, is formed at the same time to have a uniform thickness. Although formed to have a uniform thickness, even the most exacting fabrication processes produce a variation in the thickness of the dielectric layer, with some regions thicker and other regions thinner.
However, thinner regions of the dielectric layer intensify the effect of the electric field which, in turn, intensifies the effect of the source GIDL component of the dark current. In some cases, the source GIDL component, along with the intensified effect from the thinner regions of the dielectric material, cause significant numbers of the cells in the array to saturate before the integration period has ended.
These saturated active pixel sensor cells, which are bad, appear as white dots in the resulting image, and seriously effect the quality of the resulting image. As a result, there is a need for a deep-submicron active pixel sensor cell that substantially reduces the magnitude of the dark current.